Method of producing a semiconductor device

ABSTRACT

In a case where a semiconductor device is produced comprising at least one semiconductor element, an isolation region surrounding the semiconductor element and a thick silicon oxide layer lying on and around the semiconductor element, the thick oxide layer is formed by thermally-oxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitaxial layer by heating for thermal oxidation. Prior to a step of introducing impurities into the epitaxial layer, a patterned thin silicon oxide layer is formed. This thin silicon oxide layer is varied into the thick oxide layer by the thermal-oxidation treatment.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for producing a semiconductordevice comprising at least one semiconductor element and an isolationregion which are formed in an epitaxial layer formed on a semiconductorsubstrate. More particularly, the present invention relates to a methodfor forming both a silicon oxide layer which lies on and around thesemiconductor element, and an isolation region which lies around thesemiconductor element and has an opposite conductivity type to that ofthe epitaxial layer.

2. Description of the Prior Art

In a case where a semiconductor integrated circuit is produced byforming semiconductor elements, such as transistors, and passiveelements, such as diffused resistors, in an epitaxial layer formed on asilicon semiconductor substrate, generally, after a silicon oxide layeris formed as a protecting layer on the surface of the integratedcircuit, connecting lines of a conductor, such as aluminum, are formedon the silicon oxide layer. In this case, in order to decrease theparasitic capacity between the epitaxial layer and the aluminumconnecting lines, the above-mentioned silicon oxide layer is made thick.Furthermore, in order to prevent a so-called parasitic effect fromoccuring between the semiconductor elements, an isolation region betweenthe semiconductor elements is formed by introducing impurities having anopposite conductivity type to that of the epitaxial layer into apredetermined portion of the epitaxial layer.

A semiconductor element (e.g. an npn-type bipolar transistor) of anintegrated circuit is illustrated in the schematic sectional view ofFIG. 1. Such a bipolar transistor is illustrated in FIG. 2 of U.S. Pat.No. 3,911,471. In FIG. 1, reference numerals 1, 2, 2' and 3 indicate ap-type silicon substrate, an n-type silicon epitaxial layer, an isolatedregion and an n-type buried layer, respectively. The electricalresistance of the epitaxial layer 2 is high and, consequently, thebreakdown voltage between the collector and the base of the bipolartransistor is high. The buried layer 3 can reduce the series resistanceof the collector. Reference numerals 4, 5, 6 and 7 indicate a p-typebase region, an n-type emitter region, an n-type collector connectingregion and an isolation region, respectively. These regions 4, 5, 6 and7 are formed in the epitaxial layer 2. Since the isolation region 7 hasthe opposite conductivity type to that of the epitaxial layer andsurrounds the isolated region 2', it is possible to electrically isolatethe bipolar transistor from other transistors and passive elements (notshown). Reference numerals 8, 8A through 8C, 9, 10 and 11 indicate asilicon oxide layer, thick portions of the silicon oxide layer, acollector electrode, a base electrode and an emitter electrode,respectively. The thick portions 8A, 8B and 8C of the silicon oxidelayer 8 decrease the parasitic capacitance between the epitaxial layerand the connecting lines of the electrodes 9, 10 and 11. According toFIG. 1 the thick portions of the silicon oxide layer are separated, butthe thick portions may be combined in a manner not shown in FIG. 1.

The bipolar transistor illustrated in FIG. 1 is produced in thefollowing manner. Referring to FIG. 2, the starting material is a p-typesilicon semiconductor substrate 1. N-type impurities are introduced intoa predetermined portion of the silicon substrate 1 by ion-implantationor thermal diffusion to form a buried layer 3. An n-type siliconepitaxial layer 2 is formed on the silicon substrate 1 by epitaxialgrowth and, at the same time, some impurities diffuse out of the buriedlayer 3 into the epitaxial layer 2, so that the buried layer 3 expandsup to a broken line in FIG. 2. A silicon nitride layer serving as ananti-oxidation masking layer is formed on the epitaxial layer 2 bychemical vapor deposition and, then, is selectively removed byphotoetching, so that portions 12A, 12B and 12C of the silicon nitridelayer remain, as illustrated in FIG. 2. If desired, a thin oxide layermay be provided under the silicon nitride layer.

Next, the semiconductor body comprising the silicon substrate 1 and thesilicon epitaxial layer 2 is thermally oxidized at 1000° C. forapproximately 2 hours. Since the silicon nitride layer portions 12A, 12Band 12C serve as an anti-oxidation mask during the oxidation period, asilicon dioxide (SiO₂) layer 13 having a thickness of approximately 700nm is formed, as illustrated in FIG. 3.

The formed silicon dioxide layer 13 is removed by etching to expose aportion of the epitaxial layer 2. Then, the semiconductor body is alsothermally oxidized at 1000° C. for approximately 8 hours to form a thicksilicon dioxide layer 14 having a thickness of approximately 1.4 μm, asillustrated in FIG. 4.

Next, a photoresist layer (not shown) is applied on the entire surfaceand, then, a portion of the resist layer which lies on the siliconnitride layer portion 12A is removed. P-type impurities are introducedthrough the silicon nitride layer portion 12A into the epitaxial layer 2by ion-implantation to form a high concentration region 15 of p-typeimpurities, as illustrated in FIG. 5. After the applied resist layer isremoved, another photoresist layer is applied onto the entire surface,and then, a portion of the resist layer which lies on the siliconnitride layer portion 12B is removed. N-type impurities are introducedthrough the silicon nitride layer portion 12B into a portion of theepitaxial layer 2 by ion-implantation to form a high concentrationregion 16 of n-type impurities, as illustrated in FIG. 5.

The obtained semiconductor body is heated at 1100° C. for approximately1 hour, whereby the p-type impurities in the high concentration regions15 diffuse into the epitaxial layer 2 and arrive at the siliconsubstrate 1 to form an isolation region 7 for isolating semiconductorelements from each other and, at the same time, the n-type impurities inthe high concentration region 16 diffuse and arrive at the buried layer3 to form a collector connecting region 6, as illustrated in FIG. 6.

Next, the remaining silicon nitride layer portions 12A, 12B and 12C areremoved to expose portions of the epitaxial layer 2. The obtainedsemiconductor body is thermally oxidized at 900° C. for approximately 30minutes to form a thin silicon dioxide layer 8, having a thickness ofapproximately 50 nm, on the surfaces of the exposed portions of theepitaxial layer including the isolation region 7 and the collectorconnecting region 6, as illustrated in FIG. 7. A patterned photo resistlayer 17 is formed on the thin and thick silicon dioxide layers 8 and14, as illustrated in FIG. 7. P-type impurities are introduced through aportion of the thin silicon dioxide layer 8 into a portion of theisolated region 2' of the epitaxial layer 2 by ion-implantation to forma high concentration region 18 of the p-type impurities.

The obtained semiconductor body is annealed by heating at 1000° C. forapproximately 10 minutes, whereby the impurities in the highconcentration region 18 diffuse to a predetermined depth in theepitaxial layer 2, so that a base region 5 is formed, as illustrated inFIG. 8. Then, N-type impurities are introduced into a portion of thebase region 5 by ion-implantation subsequent to etching of a portion ofthe thin silicon dioxide layer lying on the base region 5 byphotoetching. An annealing treatment is carried out at 1000° C. forapproximately 20 minutes to form an emitter region 4, as illustrated inFIG. 1.

Openings for the collector electrode 9 and for the base electrode 11 areformed in the thin silicon dioxide layer above the collector connectingregion 6 and the base region 5, respectively, by photoetching, asillustrated in FIG. 1. Finally, a conductor layer of aluminum is formedon the entire surface by vapor deposition and, then, is selectivelyremoved by photoetching to form the collector, base and emitterelectrodes 9, 11 and 10, respectively. In the above described manner, annpn-type bipolar transistor isolated from other elements is produced, asillustrated in FIG. 1.

However, when the thick silicon dioxide layer 14 (FIG. 4) is formedprior to the introduction of impurities into the epitaxial layer 2, aportion of the epitaxial layer lying under the silicon nitride layerportions 12A, 12B and 12C is oxidized into silicon dioxide. Namely, aportion of the thick silicon dioxide layer 14 enters under the siliconnitride layer portions to form a so-called bird's beak, as illustratedin FIG. 4. Since the bird's beak of silicon dioxide prevents theimpurities from entering into the epitaxial layer 2, for example, inorder to form the isolation region 7 having a width of 1 μm, it isnecessary to make the width of the silicon nitride layer portion 12Aapproximately 3 μm. As the width of the silicon nitride layer portion12A increases, on the one hand, its area increases, and on the otherhand, the area for semiconductor elements and passive elements of theintegrated circuit decreases. Therefore, it is difficult to increase thedegree of integration of the semiconductor elements and the passiveelements in the integrated circuit.

Furthermore, according to the above-mentioned production method, themethod comprises the step of forming the thick silicon dioxide layer,and the step of diffusing the impurities for forming the isolationregion and the collector connecting region, namely, a heat-treatment iscarried out at least two times. When the heat-treatment is repeated, theimpurities in the buried layer diffuse upward in the epitaxial layer. Asthe result of this, the breakdown voltage between the collector and theemitter decreases.

SUMMARY OF THE INVENTION

It is an object of the present invention to increase the degree ofintegration of semiconductor elements and passive elements in anintegrated circuit over that of the prior art and to prevent thebreakdown voltage between the collector and the base of a bipolartransistor from decreasing, by providing an improved method forproducing a semiconductor device comprising at least one semiconductorelement and an isolation region which are formed in an epitaxial layerformed on a semiconductor substrate.

The present invention is based on recognition of the fact that (1), in acase where impurities are introduced into the epitaxial layer prior tothe step of forming a thick oxide layer by thermal oxidation, anintegrated circuit design (i.e. the shapes and dimensions of thesemiconductor elements, the passive elements and the isolation region)can be determined without having to take into consideration a bird'sbeak of the thick oxide layer, and that (2) a formation step of thethick oxide layer and a formation step of the isolation region can becarried out in one heat treatment.

According to the present invention, a method of producing asemiconductor device comprising at least one semiconductor element andan isolation region, which are formed in an epitaxial layer formed on asemiconductor substrate having a buried layer, comprises the steps of:

forming an anti-oxidation masking layer on the epitaxial layer;

selectively removing the masking layer by photoetching to exposeportions of the epitaxial layer;

thermally oxidizing the exposed portions of the epitaxial layer to forma thin oxide layer;

forming a patterned resist layer;

introducing impurities into a predetermined portion of the epitaxiallayer which is covered by the masking layer and is not under the resistlayer;

removing the patterned resist layer; and

thermally oxidizing the epitaxial layer by using the remaininganti-oxidation masking layer as a mask to form a thick oxide layer, atthe same time the introduced impurities are diffused into the epitaxiallayer to form the isolation region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view of a prior art bipolar transistorof an integrated circuit;

FIGS. 2 through 8 are schematic sectional views of the bipolartransistor of FIG. 1 in intermediate stages of production in accordancewith prior art techniques;

FIGS. 9 through 13 are schematic sectional views of a bipolar transistorin intermediate stages of production in accordance with an embodiment Aof the present invention;

FIGS. 14 and 15 are schematic sectional views of a bipolar transistor inintermediate stages of production in accordance with an embodiment B ofthe present invention;

FIGS. 16 and 17 are schematic sectional views of a bipolar transistor inintermediate stages of production in accordance with the embodiment C ofthe present invention;

FIGS. 18 and 19 are schematic sectional views of a bipolar transistor inintermediate stages of production in accordance with an embodiment D ofthe present invention;

FIGS. 20 through 22 are scematic sectional views of a bipolar transistorin intermediate stages of production in accordance with combinations ofthe other embodiments;

FIG. 23 is a schematic sectional view of a bipolar transistor in anintermediate stage of production in accordance with a variantcombination of the embodiments;

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be explained in detail by the followingembodiments A through D with reference to the drawings.

Embodiment A

Referring to FIG. 9, the starting material is a p-type siliconsemiconductor substrate 21. N-type impurities (e.g. antimony) areintroduced into a predetermined portion of the silicon substrate 21 toform an n⁺ -type buried layer 22. An n-type silicon epitaxial layer 23,having a high resistance, is formed on the silicon substrate 21 and, atthe same time, some n-type impurities diffuse out of the buried layer 22into the epitaxial layer 23, so that the buried layer 22 expands up to abroken line in FIG. 9. A silicon nitride layer having a thickness ofapproximately 50 nm and serving as an anti-oxidation masking layer isformed on the epitaxial layer 23 by chemical vapor deposition, and then,is selectively removed by photoetching so that portions 24A, 24B and 24Cof the silicon nitride layer remain, as illustrated in FIG. 9.

Next, the semiconductor body comprising the silicon substrate 21 and theepitaxial layer 23 is heated at 1000° C., for approximately 2 hours, inan oxidizing atmosphere. As the result, the portion of the epitaxiallayer 23 which is not covered by the silicon nitride layer portions 24A,24B and 24C is oxidized to form a thin silicon dioxide layer 25 having athickness of approximately 700 nm, as illustrated in FIG. 10.

A photo resist layer 26 is applied on the entire surfaces of the siliconnitride layer portions 24A, 24B and 24C, and the thin silicon dioxidelayer 25, and then, is selectively etched to remove a portion of itwhich lies on the silicon nitride layer portion 24A, as illustrated inFIG. 11. P-type impurities (e.g. boron) are introduced through thesilicon nitride layer portion 24A into the epitaxial layer 23 byion-implantation to form a high concentration region 27 (FIG. 11) ofp-type impurities.

After the photo resist layer 26 is removed, another photo resist layer28 is applied onto the entire surfaces of the layer portions 24A, 24Band 24C, and the layer 25, and then, is selectively etched to remove aportion of it which lies on the silicon nitride layer portion 24B, asillustrated in FIG. 12. N-type impurities (e.g. phosphorus) areintroduced through the silicon nitride layer 24B into the epitaxiallayer 23 by ion-implantation to form a high concentration region 29(FIG. 12) of n-type impurities. The photo resist layer 28 is thenremoved.

Next, the obtained semiconductor body is heated at 1000° C., forapproximately 6 hours, in the oxidizing atmosphere. As a result of theheat-treatment, i.e. a thermal oxidation treatment, the thickness of thethin silicon dioxide layer 25 increases to form a thick silicon dioxidelayer 30 having a thickness of approximately 1.4 μm, the p-typeimpurities in the high concentration region 27 diffuse into theepitaxial layer 23 and arrive at the silicon substrate 21 to form anisolation region 31 and, simultaneously, the n-type impurities in thehigh concentration region 29 diffuse and arrive at the buried layer 22to form a collector connecting region 32, as illustrated in FIG. 13.

Thus, since the formation of the thick silicon dioxide layer, theisolation region and the collector connecting region are simultaneouslycarried out, the number of heat-treatments is decreased as compared withthe above-mentioned prior art method of producing a semiconductordevice. Therefore, the decrease in the breakdown voltage between thecollector and the base caused by diffusing the n-type impurities out ofthe buried layer into the epitaxial layer is smaller than in the priorart.

In order to complete a bipolar transistor, a base region, an emitterregion, a collector electrode, a base electrode, an emitter electrodeand a required thin silicon dioxide layer are formed in the same manneras in the above-mentioned prior art method.

Embodiment B

Prior to the step of forming the thin silicon dioxide layer 25 (FIG. 10)of the embodiment A of the present invention, a portion of the epitaxiallayer 23 can be etched by an etchant (e.g., HF:HNO₃ AgNO₃ =5:40:1), asillustrated in FIG. 14. In this case, the silicon nitride layer portions24A, 24B and 24C serve as a mask, and the etching depth is approximately300 nm. Furthermore, the etching of the epitaxial layer can be carriedout by a plasma etching process. In this case, a photoresist layer (notshown) is applied onto the silicon nitride layer subsequent to formationof the silicon nitride layer and, then, is exposed and developed. Sinceall of the silicon nitride layer, except for its portions 24A, 24B and24C, is exposed, the exposed portion of the silicon nitride layer andthe portion of the epitaxial layer thereunder can be etched by plasma.Then, the obtained semiconductor body is treated in the same manner asin method of the embodiment A to obtain the semiconductor body in thestate illustrated in FIG. 15.

The difference between the levels of the surface of the thick silicondioxide layer 30 (FIG. 15) and the surface of the epitaxial layer 23(FIG. 15) is smaller as compared with that of the semiconductor body inthe state illustrated in FIG. 13, in the case of the embodiment A.

Embodiment C

Subsequent to the step of forming the photoresist layer 26 (FIG. 11) andprior to the step of introducing the impurities of the embodiment A, thesilicon nitride layer portion 24A can be etched as illustrated in FIG.16. Therefore, the p-type impurities can be directly introduced into anexposed portion of the epitaxial layer 23. The procedure for producing asemiconductor device in this embodiment, except for the above-mentionedetching step is same as that of the embodiment A. As the result, thesemiconductor body in the state illustrated in FIG. 17 is obtained. Aportion of the thick silicon dioxide layer 29 is formed on the isolationregion 31, whereby the parasitic capacitance between a connecting lineand the isolation region can be decreased.

Embodiment D

Subsequent to the step of removing the photo resist 28 (FIG. 12) of theembodiment A, the thin silicon dioxide layer 25 (FIG. 12) can be etchedby an aqueous solution of hydrofluoric acid, as illustrated in FIG. 18.Then, the obtained semiconductor body is heated under the sameconditions as those of the heating step of the embodiment A, so that anexposed portion of the epitaxial layer 23 is oxidized to form a thicksilicon dioxide layer 33 having a thickness of approximately 1.4 μm, asillustrated in FIG. 19. At the same time, the isolation region 31 andthe collector connecting region 32 are formed. Since the surfaces of theepitaxial layer 23 and the thick silicon dioxide layer 33 are almostflat, it is possible to produce a planar type bipolar transistor.

Furthermore, it is possible to combine the above-mentioned embodimentsB, C and D. For example, a combination of the embodiments B and C and acombination of the embodiments C and D can be carried out. In a casewhere the embodiments B and C are combined, subsequent to the step offorming the high concentration region 27 and prior to the step offorming the photo resist layer 28 of the embodiment A, the semiconductorbody in the state illustrated in FIG. 20 is obtained. As a result, afterthe thermal oxidation for the thick silicon dioxide layer 30 is carriedout, the semiconductor body in the state illustrated in FIG. 21 isobtained. In a case where the embodiments C and D are combined, thesemiconductor body in the state illustrated in FIG. 21 is also obtainedvia the state illustrated in FIG. 22. The above-mentioned combinationsof the embodiments can further include the step of etching a portion ofthe epitaxial layer corresponding to the isolation region subsequent tothe step of etching the silicon nitride layer portion of the embodimentC. As a result, the semiconductor body in the state illustrated in FIG.23 is obtained.

In the embodiment A, a photo etching technique (i.e. photo lithography)is used, but an electron beam lithography, an ion beam lithography or anX-ray lithography may be used.

Furthermore, in a case where the length of the thick silicon dioxideportion 8C (FIG. 1), namely, the distance between the isolation region 7and the base region 4 (FIG. 1) is 2 μm and below, the punch throughphenomenon after occurs, when a depletion layer extending from the baseregion-exitaxial layer interface into the isolated region 2' (FIG. 1) isjoined to a depletion layer extending from the isolationregion-epitaxial layer interface into the isolated region 2'. The punchthrough phenomenon generates an undesirable leakage current. In order toprevent the punch through phenomenon from occurring, it is preferable tointroduce n-type impurities (a dose of 5×10¹² atoms/cm² at an energy of60 KeV) into a portion of the epitaxial layer 2 lying under the silicondioxide layer portion 8C by ion-implantation prior to the step offorming the thick silicon dioxide layer portion 8C.

It will be obvious that the present invention is not restricted to theabove-mentioned embodiments, and that many variations are possible forthose skilled in the art without departing from the scope of the presentinvention. For example, it is possible to produce a pnp-type bipolartransistor instead of the npn-type bipolar transistor. An anti-oxidationmasking layer may be made of silicon carbide instead of silicon nitride.

We claim:
 1. A method of producing a semiconductor device comprising atleast one bipolar transistor and an isolation region which are formed inan epitaxial layer formed on a semiconductor substrate having a buriedlayer, said method comprising, in sequence, the steps of:forming ananti-oxidation masking layer on said epitaxial layer, selectivelyremoving said masking layer by etching to expose portions of saidepitaxial layer, thermally oxidizing said exposed portions of theepitaxial layer to form a thin oxide layer, introducing a first impurityinto a first predetermined portion of said epitaxial layer correspondingto said isolation region by using a first patterned resist layer as amask, introducing a second impurity through said masking layer into asecond predetermined portion of said epitaxial layer corresponding to acollector-connecting-region of the bipolar transistor by using a secondpatterned resist layer as a mask, thermally oxidizing said epitaxiallayer by using the remaining anti-oxidation masking layer as to mask toform a thick oxide layer, while at the same time diffusing saidintroduced first and second impurities into said epitaxial layer to formsaid isolation region and said collector-connecting-region coming intocontact with said buried layer, respectively, and forming a base regionand an emitter region of the bipolar transistor in a portion of saidepitaxial layer above said buried layer.
 2. The method of claim 1,wherein said substrate has the conductivity type of said first impuritytype.
 3. The method of claim 1 or 2, comprising the step of etching saidexposed portions of the epitaxial layer prior to the formation of thethin oxide layer.
 4. The method of claim 1 or 2, wherein said firstimpurity for said isolation region is introduced through a selectedremaining portion of said masking layer.
 5. The method of claim 1 or 2,wherein said first impurity for said isolation region is directlyintroduced into the respective portion of said epitaxial layer, after aportion of said masking layer on said respective portion of theepitaxial layer is removed by etching by using said first resist layeras a mask.
 6. The method of claim 1 or 2, comprising the step ofremoving said thin oxide layer prior to said forming of the thick oxidelayer and subsequent to said introducing of said second impurity. .Iadd.7. A method of producing a semiconductor device comprising at least onesemiconductor element and an isolation region, which are formed in anepitaxial layer formed on a semiconductor substrate having a buriedlayer, comprising the steps of;forming an anti-oxidation masking layeron the epitaxial layer; selectively removing the masking layer byetching to uncover portions of the epitaxial layer; thermal-oxidizingthe exposed portions of the epitaxial layer to form a thin oxide layer;forming a patterned resist layer to selectively cover said maskinglayer; introducing impurities into a predetermined portion of theepitaxial layer which is not under the resist layer; removing thepatterned resist layer; and thermal-oxidizing the epitaxial layer byusing the remaining anti-oxidation masking layer as a mask to form athick oxide layer, at the same item the introduced impurities arediffused into the epitaxial layer to form the isolation region..Iaddend.